1. Field of the Invention
The present invention relates to an output circuit for outputting signals, designed for use in a semiconductor integrated circuit.
2. Description of the Related Art
In electronic apparatuses such as 1-chip computers, signals are transferred through a common bus line. FIG. 1 illustrates a typical electrical connection applied in bus-line application. As shown in, FIG. 1, two tri-state buffers 501 and 502 are connected to a bus line 500. The buffers 501 and 502, which are output circuits, output one signal each. Both tri-state buffers are of CMOS structure. When the enable signals EN1 and EN2 input to them are made active, they generate from the signals IN1 and IN2 two signals, which are output to the bus line 500. When the enable signals EN1 and EN2 are inactive, the outputs of both buffers 501 and 502 are in high-impedance state. Assume that different power-supply potentials VCC1 and VCC2 are applied to the tri-state buffers 501 and 502. Either tri-state buffer has an intrinsic diode 503 which has its cathode connected to the power supply and its anode connected to the output node.
As mentioned above the tri-state buffers 501 and 502 are of CMOS structure. As shown in FIG. 2, either tri-state buffer has a P-channel MOS transistor 511 and an N-channel MOS transistor 512 in the output stage. The P-channel MOS transistor 511 receives a gate control signal generated by a NAND gate 514 supplied with an input signal IN and an output of an inverter 513 which inverts an enable signal EN. The N-channel MOSFET 512 receives a gate control signal generated by a NOR gate 515 supplied with the input signal IN and the enable signal EN. The P-type drain diffusion layer of the P-channel MOS transistor 511 and the N-type drain diffusion layer of the N-channel MOSFET 512 are connected to the output node 516 of the tri-state buffer. A pn-junction diode 517 is connected between the output node 516 and the back gate of the P-channel MOS transistor 511. This pn-Junction diode is the parasitic diode 503 shown in FIG. 1.
Assume that the tri-state buffer 502 shown in FIG. 1 outputs a high-level signal, whereas the tri-state buffer 501 is in the high-impedance state. If VCC1&lt;VCC2-Vf, where vf is the built-in potential of the parasitic pn-Junction diode provided between the drain diffusion layer and back gate of the P-channel MOS transistor 511, the diode 503 is therefore forwardly biased. Consequently, a current I flows from the source of the potential VCC2 to the source of the power-supply potential VCC1 through the parasitic pn-Junction diode as is illustrated in FIG. 1.
To prevent the current I from flowing so, the output stage connected to the output node 516 may be constituted by exclusively N-channel MOS transistors. An output stage formed of N-channel MOS transistors only is shown in FIG. 3. This output stage of a tri-state buffer comprises two N-channel MOS transistors 518 and 512. The N-channel MOS transistor 518 receives a gate control signal generated by a NOR gate 519 supplied with an enable signal EN and an output of an inverter 513 which inverts an input signal IN. The MOS transistor 512 receives a gate control signal generated by a NOR gate 515 supplied with the input signal IN and the enable signal EN, as in the tri-state buffer shown in FIG. 2. The buffer of FIG. 3, whose output stage is made up of N-channel MOS transistors only, can output the ground potential from the output node 516. However, it cannot output the power-supply potential VCC. Its output signal level inevitably lowers by the threshold voltage of the N-channel MOS transistors.
As indicated above, if different power-supply potentials are applied to output circuits connected to a common bus line, a current unavoidably flows between the sources of the power supply potentials. To prevent this flow of a current, the output stages of the output circuits may may be constituted by exclusively N-channel MOS transistors each. If so, the output signal of each output circuit will fail to swing fully.